FIB Circuit Edit

ADVANCED FIB CIRCUIT EDIT

Front and Backside FIB Circuit modification services | Backside Sample Preparation

ACE offers both Frontside and Backside FIB Circuit Edit down to 7nm process tech-nodes.

FIB Circuit Edit offers quick-fix IC debug verification of design changes within initial flawed silicon runs.  FIB modifications allow for disconnecting of IC metal traces, multiple jumper connections, post packaged flip-chip “backside fib circuit edit” as well as probe-pad node access deposition for electrical testing.  Utilizing advanced proprietary techniques, we are able to perform IC modifications down to 7nm.

RESULTS

  • Proven 7nm FIB circuit edit success.
  • Front & Backside FIB circuit edits.
  • 12″ full wafer FIB edit.
  • FIB nano-machining

COMPETITIVELY PRICED

  • Discounts for volume work.
  • No “rush-surcharge” expedite fees and free weekend work.
  • Quick turn-around.
  • Free local delivery and pickup services

Free consultation

  • Free layout FIB design.
  • Our engineers will work with you and your team on implementing the highest FIB yield design to achieve your circuit edit goals.

CAPABILITIES AND INFORMATION

FIB Cross section Lamella prep Nanolab 660
FIB CIRCUIT EDIT

ADVANCED CAPABILITIES

7nm FinFET, 14/16nm FinFET, 28nm: Front & Backside FIB circuit edits.

STANDARD CAPABILITIES

40nm, 45nm, 65nm, .13um, .18um, .25um, .35um: Front & Backside FIB circuit modification.

EXPERIENCE / YIELD

Over 50-years experience (+ 50,000 hours) techniques and innovative FIB circuit edit expertise.

PACKAGE TYPE

BGA, QFN, CSP, WLBGA, 8″ wafer, packaged “flip-chip”, die level

WAFER SIZE ACCOMMODATIONS

  • 4″, 6″, 8″ and 12″ wafer.
  • 300mm (12″ full-wafer) FIB Circuit edit

BACKSIDE SAMPLE PREPARATION

Mechanical polish of bulk SI down to ~100um for flip-chip “backside” editing.

FIB Gallery